LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.conversions.all; ENTITY Test_Bench IS END Test_Bench; ARCHITECTURE Test_Bench_Arch OF Test_Bench IS SIGNAL clk : std_logic; SIGNAL out1_vec : std_logic_vector(3 downto 0); SIGNAL out2_vec : std_logic_vector(3 downto 0); SIGNAL out_chip_vec : std_logic_vector(3 downto 0); SIGNAL in_vec : std_logic_vector(3 downto 0); SIGNAL in_chip_vec : std_logic_vector(3 downto 0); COMPONENT Chip1 PORT ( in_vec : in std_logic_vector (3 downto 0); out_vec : out std_logic_vector (3 downto 0) ); END COMPONENT; FOR instance_1:Chip1 USE ENTITY work.Chip1(Chip1_Arch); COMPONENT Stimulus PORT ( clk : in std_logic; in_vec : out std_logic_vector (3 downto 0) ); END COMPONENT; FOR instance_2:Stimulus USE ENTITY work.Stimulus(Stimulus_Arch); COMPONENT Clock PORT ( clk : out std_logic ); END COMPONENT; FOR instance_3:Clock USE ENTITY work.Clock(Clock_Arch); BEGIN in_chip_vec<='0' & in_vec (3 downto 1); instance_1: Chip1 PORT MAP (in_chip_vec , out_chip_vec); out1_vec<="000" & out_chip_vec (3); out2_vec<=out_chip_vec(2 downto 0) & in_vec(0); instance_2: Stimulus PORT MAP (clk, in_vec); instance_3: Clock PORT MAP (clk); END Test_Bench_Arch;