LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.conversions.all; ENTITY Stimulus IS PORT ( clk : in std_logic; in_vec : out std_logic_vector (7 downto 0) ); END Stimulus; ARCHITECTURE Stimulus_Arch OF Stimulus IS SIGNAL buffer_1 : std_logic_vector (7 downto 0) := "00000000"; BEGIN in_vec <= buffer_1; Stimulus :PROCESS BEGIN WHILE true LOOP WAIT UNTIL (clk'EVENT and clk = '1'); WAIT FOR 12 ns; buffer_1 <= to_vector(8,to_unsigned(buffer_1) + 1); WAIT FOR 50 ns; END LOOP; END PROCESS; END Stimulus_Arch;