LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.conversions.all; ENTITY Test_Bench IS END Test_Bench; ARCHITECTURE Test_Bench_Arch OF Test_Bench IS SIGNAL clk : std_logic; SIGNAL out1_vec : std_logic_vector(3 downto 0); SIGNAL out2_vec : std_logic_vector(3 downto 0); SIGNAL out3_vec : std_logic_vector(3 downto 0); SIGNAL out1_chip_vec : std_logic_vector(3 downto 0); SIGNAL out2_chip_vec : std_logic_vector(3 downto 0); SIGNAL out3_chip_vec : std_logic_vector(3 downto 0); SIGNAL out4_chip_vec : std_logic_vector(3 downto 0); SIGNAL out5_chip_vec : std_logic_vector(3 downto 0); SIGNAL out6_chip_vec : std_logic_vector(3 downto 0); SIGNAL out7_chip_vec : std_logic_vector(3 downto 0); SIGNAL in_vec : std_logic_vector(7 downto 0); SIGNAL in1_chip_vec : std_logic_vector(3 downto 0); SIGNAL in2_chip_vec : std_logic_vector(3 downto 0); SIGNAL in3_chip_vec : std_logic_vector(3 downto 0); SIGNAL in4_chip_vec : std_logic_vector(3 downto 0); SIGNAL in5_chip_vec : std_logic_vector(3 downto 0); SIGNAL in6_chip_vec : std_logic_vector(3 downto 0); SIGNAL in7_chip_vec : std_logic_vector(3 downto 0); COMPONENT Chip1 PORT ( in_vec : in std_logic_vector (3 downto 0); out_vec : out std_logic_vector (3 downto 0) ); END COMPONENT; FOR instance_1:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_2:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_3:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_4:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_5:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_6:Chip1 USE ENTITY work.Chip1(Chip1_Arch); FOR instance_7:Chip1 USE ENTITY work.Chip1(Chip1_Arch); COMPONENT Stimulus PORT ( clk : in std_logic; in_vec : out std_logic_vector (7 downto 0) ); END COMPONENT; FOR instance_8:Stimulus USE ENTITY work.Stimulus(Stimulus_Arch); COMPONENT Clock PORT ( clk : out std_logic ); END COMPONENT; FOR instance_9:Clock USE ENTITY work.Clock(Clock_Arch); BEGIN in1_chip_vec<='0' & in_vec (7 downto 5); instance_1: Chip1 PORT MAP (in1_chip_vec , out1_chip_vec); in2_chip_vec<=out1_chip_vec (2 downto 0) & in_vec(4); instance_2: Chip1 PORT MAP (in2_chip_vec , out2_chip_vec); in3_chip_vec<=out2_chip_vec (2 downto 0) & in_vec(3); instance_3: Chip1 PORT MAP (in3_chip_vec , out3_chip_vec); in4_chip_vec<='0' & out1_chip_vec (3) & out2_chip_vec(3) & out3_chip_vec(3); instance_4: Chip1 PORT MAP (in4_chip_vec , out4_chip_vec); in5_chip_vec<=out3_chip_vec (2 downto 0) & in_vec(2); instance_5: Chip1 PORT MAP (in5_chip_vec , out5_chip_vec); in6_chip_vec<=out4_chip_vec (2 downto 0) & out5_chip_vec(3); instance_6: Chip1 PORT MAP (in6_chip_vec , out6_chip_vec); in7_chip_vec<=out5_chip_vec (2 downto 0) & in_vec(1); instance_7: Chip1 PORT MAP (in7_chip_vec , out7_chip_vec); out1_vec<="00" & out4_chip_vec (3) & out6_chip_vec (3); out2_vec<=out6_chip_vec(2 downto 0) & out7_chip_vec(3); out3_vec<=out7_chip_vec(2 downto 0) & in_vec(0); instance_8: Stimulus PORT MAP (clk, in_vec); instance_9: Clock PORT MAP (clk); END Test_Bench_Arch;