Chip1.vhd

LIBRARY ieee;
USE     ieee.std_logic_1164.all;
USE 	work.conversions.all;

LIBRARY SYNTH;
USE SYNTH.VIEWARCHITECT.ALL;

ENTITY Chip1 is 
PORT	(
	in_vec	 : in std_logic_vector (3 downto 0);
	out_vec : out std_logic_vector (3 downto 0)
	);
END Chip1;

ARCHITECTURE Chip1_Arch OF Chip1 IS
BEGIN
  b2b:	PROCESS (in_vec)
  BEGIN
		CASE in_vec IS
			WHEN "0000"=>out_vec<="0000";
			WHEN "0001"=>out_vec<="0001";
			WHEN "0010"=>out_vec<="0010";
			WHEN "0011"=>out_vec<="0011";
			WHEN "0100"=>out_vec<="0100";
			WHEN "0101"=>out_vec<="1000";
			WHEN "0110"=>out_vec<="1001";
			WHEN "0111"=>out_vec<="1010";
			WHEN "1000"=>out_vec<="1011";
			WHEN "1001"=>out_vec<="1100";
			WHEN others =>out_vec<="1111";
     END CASE;
  END PROCESS b2b;
END Chip1_Arch;