Clock.vhd

LIBRARY	ieee;
USE	ieee.std_logic_1164.all;
ENTITY Clock  IS
PORT	(
	clk	: out std_logic
	);
END Clock;
     
ARCHITECTURE Clock_Arch OF Clock IS

BEGIN
  ticker:	PROCESS
  BEGIN
    clk <= '1';
    WAIT FOR 25 ns;
    clk <= '0';
    WAIT FOR 25 ns;
  END PROCESS ticker;
END Clock_Arch;